Kegang K Huang from Fremont, CA, age 62Get Report

Fremont, CA

Kegang Huang Phones & Addresses

  • 49198 Violet Ter, Fremont, CA 94539 (510) 445-1780
  • 44100 Packard Ct, Fremont, CA 94539 (510) 490-7127
  • Sacramento, CA
  • Upton, NY
  • Middle Island, NY
  • Sunnyvale, CA
  • Union City, CA
  • Alameda, CA
  • Beaverton, OR
  • San Antonio, TX

Resumes

Resumes

Sr. Mts At Spatial Photonics, Inc.

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Kegang Huang Photo 1
Position:
Sr. MTS at Spatial Photonics, Inc.
Location:
San Francisco Bay Area
Industry:
Semiconductors
Work:
Spatial Photonics, Inc.
Sr. MTS
Education:
Ph.D.

Manager, Mems Yield And Reliability At Invensense, Inc.

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Kegang Huang Photo 2
Position:
Manager, MEMS Yield and Reliability at InvenSense, Inc.
Location:
San Francisco Bay Area
Industry:
Semiconductors
Work:
InvenSense, Inc.
Manager, MEMS Yield and Reliability

Manager, Mems Reliability And Yield At Invensense, Inc.

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Kegang Huang Photo 3
Location:
San Francisco Bay Area
Industry:
Semiconductors

Publications

Us Patents

Method Of Making A Transistor, In Particular Spacers Of The Transistor

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US Patent:
6566183, May 20, 2003
Filed:
Dec 12, 2001
Appl. No.:
10/017192
Inventors:
Steven A. Chen - San Jose CA,
Lee Luo - Fremont CA,
Kegang Huang - Fremont CA,
Tzy-Tzan Fu - Hsin-Chu 300,
Kuan-Ting Lin - Keelung,
Hung-Chuan Chen - Hsin-Chu 300,
International Classification:
H01L 218238
US Classification:
438230, 438595, 438791
Abstract:
The invention provides a method of making a transistor. A gate dielectric layer is formed on a semiconductor substrate. A gate is formed on the dielectric layer, the gate having an exposed upper surface and exposed side surfaces. A first silicon nitride layer having a first thickness is deposited over the gate, for example over an oxide layer on the gate, at a first deposition rate. A second silicon nitride layer having a second thickness is deposited over the first silicon nitride layer at a second deposition rate, the second thickness being more that the first thickness and the second deposition rate being more than the first deposition rate. The first silicon nitrogen layer then has a lower hydrogen concentration. At least the second silicon nitride layer (or a silicon oxide layer in the case of an ONO spacer) is etched to leave spacers next to the side surfaces while exposing the upper surface of the gate and areas of the substrate outside the spacers.

Reduction Of Hillocks Prior To Dielectric Barrier Deposition In Cu Damascene

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US Patent:
7723228, May 25, 2010
Filed:
May 20, 2003
Appl. No.:
10/442359
Inventors:
Nagarajan Rajagopalan - Santa Clara CA,
Meiyee Shek - Mountain View CA,
Kegang Huang - Fremont CA,
Bok Hoen Kim - San Jose CA,
Hichem M'saad - Santa Clara CA,
Thomas Nowak - Cupertino CA,
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/4763
US Classification:
438637, 257E21293
Abstract:
Unwanted hillocks arising in copper layers due to formation of overlying barrier layers may be significantly reduced by optimizing various process parameters, alone or in combination. A first set of process parameters may be controlled to pre-condition the processing chamber in which the barrier layer is deposited. A second set of process parameters may be controlled to minimize energy to which a copper layer is exposed during removal of CuO prior to barrier deposition. A third set of process parameters may be controlled to minimize the thermal budget after removal of the copper oxide.

Method Of Preventing Stiction Of Mems Devices

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US Patent:
2012031, Dec 13, 2012
Filed:
Jun 5, 2012
Appl. No.:
13/489380
Inventors:
Kegang HUANG - Fremont CA,
Martin LIM - San Mateo CA,
Xiang LI - Mountain View CA,
Assignee:
INVENSENSE, INC. - Sunnyvale CA
International Classification:
H01L 29/84
H01L 21/02
US Classification:
257415, 438 50, 257E29324, 257E21002
Abstract:
A method and apparatus are disclosed for reducing stiction in MEMS devices. The method comprises patterning a CMOS wafer to expose Titanium-Nitride (TiN) surface for a MEMS stop and patterning the TiN to form a plurality of stop pads on the top metal aluminum surface of the CMOS wafer. The method is applied for a moveable MEMS structure bonded to a CMOS wafer. The TiN surface and/or plurality of stop pads minimize stiction between the MEMS structure and the CMOS wafer. Further, the TiN film on top of aluminum electrode suppresses the formation of aluminum hillocks which effects the MEMS structure movement.

Reduction Of Hillocks Prior To Dielectric Barrier Deposition In Cu Damascene

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US Patent:
2008007, Mar 27, 2008
Filed:
Oct 22, 2007
Appl. No.:
11/876680
Inventors:
Nagarajan Rajagopalan - Santa Clara CA,
Meiyee Shek - Mountain View CA,
Kegang Huang - Fremont CA,
Bok Heon Kim - San Jose CA,
Hichem M'saad - Santa Clara CA,
Thomas Nowak - Cupertino CA,
Assignee:
APPLIED MATERIALS, INC. - Santa Clara CA
International Classification:
H05H 1/24
US Classification:
427579000, 427569000
Abstract:
Unwanted hillocks arising in copper layers due to formation of overlying barrier layers may be significantly reduced by optimizing various process parameters, alone or in combination. A first set of process parameters may be controlled to pre-condition the processing chamber in which the barrier layer is deposited. A second set of process parameters may be controlled to minimize energy to which a copper layer is exposed during removal of CuO prior to barrier deposition. A third set of process parameters may be controlled to minimize the thermal budget after removal of the copper oxide.

Silicon Carbide Deposition For Use As A Barrier Layer And An Etch Stop

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US Patent:
2003008, May 15, 2003
Filed:
Oct 1, 1998
Appl. No.:
09/165248
Inventors:
SUDHA RATHI - SAN JOSE CA,
PING XU - CUPERTINO CA,
CHRISTOPHER BENCHER - SUNNYVALE CA,
JUDY HUANG - LOS GATOS CA,
KEGANG HUANG - FREMONT CA,
CHRIS NGAI - BURLINGAME CA,
International Classification:
H01L021/4763
H01L021/44
H01L021/31
H01L021/469
H01L023/48
H01L023/52
H01L029/40
US Classification:
257/762000, 438/633000, 438/634000, 438/687000, 438/778000, 257/767000
Abstract:
The present invention generally provides an improved process for depositing silicon carbide, using a silane-based material with certain process parameters, onto an electronic device, such as a semiconductor, that is useful for forming a suitable barrier layer, an etch stop, and a passivation layer for IC applications. As a barrier layer, in the preferred embodiment, the particular silicon carbide material is used to reduce the diffusion of copper and may also used to minimize the contribution of the barrier layer to the capacitive coupling between interconnect lines. It may also be used as an etch stop, for instance, below an intermetal dielectric (IMD) and especially if the IMD is a low k, silane-based IMD. In another embodiment, it may be used to provide a passivation layer, resistant to moisture and other adverse ambient conditions. Each of these aspects may be used in a dual damascene structure.

Integrated Mems Devices With Controlled Pressure Environments By Means Of Enclosed Volumes

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US Patent:
8350346, Jan 8, 2013
Filed:
Jul 3, 2012
Appl. No.:
13/541306
Inventors:
Kegang Huang - Fremont CA,
Martin Lim - San Mateo CA,
Steven S. Nasiri - Saratoga CA,
Assignee:
Invensense, Inc. - Sunnyvale CA
International Classification:
H01L 29/84
US Classification:
257415, 257414, 257417, 257E29324
Abstract:
An integrated MEMS device comprises a wafer where the wafer contains two or more cavities of different depths. The MEMS device includes one movable structure within a first cavity of a first depth and a second movable structure within a second cavity of a second depth. The cavities are sealed to maintain different pressures for the different movable structures for optimal operation. MEMS stops can be formed in the same multiple cavity depth processing flow. The MEMS device can be integrated with a CMOS wafer.

Method Of Fabricating Reflective Spatial Light Modulator Having High Contrast Ratio

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US Patent:
7923789, Apr 12, 2011
Filed:
Apr 25, 2008
Appl. No.:
12/110209
Inventors:
Kegang Huang - Fremont CA,
Xiao Yang - Cupertino CA,
Dongmin Chen - Saratoga CA,
Assignee:
Miradia Inc. - Sunnyvale CA
International Classification:
H01L 27/14
US Classification:
257414, 359233
Abstract:
The contrast offered by a spatial light modulator device may be enhanced by positioning nonreflective elements such as supporting posts and moveable hinges, behind the reflecting surface of the pixel. In accordance with one embodiment, the reflecting surface is suspended over and underlying hinge-containing layer by integral ribs of the reflecting material defined by gaps in a sacrificial layer. In accordance with an alternative embodiment, the reflecting surface is separated from the underlying hinge by a gap formed in an intervening layer, such as oxide. In either embodiment, walls separating adjacent pixel regions may be recessed beneath the reflecting surface to further reduce unwanted scattering of incident light and thereby enhance contrast.

Reflective Spatial Light Modulator Having Dual Layer Electrodes And Method Of Fabricating Same

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US Patent:
7911678, Mar 22, 2011
Filed:
Dec 24, 2008
Appl. No.:
12/344172
Inventors:
Kegang Huang - Fremont CA,
Assignee:
Miradia, Inc. - Sunnyvale CA
International Classification:
G02B 26/00
G02F 1/29
US Classification:
359290, 359237, 359318
Abstract:
A reflective spatial light modulator device features two pairs of electrodes formed on different metallization layers. Elevation of the upper electrode pair reduces its distance from the overlying reflecting surface, thereby requiring a smaller applied voltage to generate an equivalent electrostatic attractive force for altering or maintaining physical orientation of the reflecting surface relative to incident light. In one embodiment, the reduced distance between the electrode and reflecting surface allows operation at lower voltages, reducing the possibility of breakdown and avoiding the need for complex device designs to eliminate such breakdown. In another embodiment, the reduced distance between the electrode and the reflecting surface allows the use of stiffer hinges for the reflecting surface, thereby increasing the speed of device operation. Other embodiments can employ both reduced voltage operation and the use of stiffer hinge structures.
Kegang K Huang from Fremont, CA, age 62 Get Report